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1 e98x34-te sony reserves the right to change products and specifications without prior notice. this information does not convey any licens e by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustr ating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. absolute maximum ratings (ta=25 c) ? supply voltage v cc 1, v cc 2 C0.3 to +5.5 v v cc 3 C0.3 to +10.0 v ? storage temperature tstg C55 to +150 c ? allowable power dissipation p d 580 mw (when mounted on a printed circuit board) operating conditions ? supply voltage v cc 1, v cc 2 4.75 to 5.30 v v cc 3 4.75 to 9.45 v ? operating temperature topr C25 to +75 c description the CXA3250N is a monolithic tv tuner ic which integrates local oscillator and mixer circuits for vhf band, local oscillator and mixer circuits for uhf band, an if amplifier and a tuning pll onto a single chip, enabling further miniaturization of the tuner. features ? low power consumption (5 v, 69 ma typ.) ? superior cross modulation ? balanced uhf oscillator (4 pins) with excellent oscillation stability ? supports both i 2 c and 3-wire bus modes ? automatic identification of 18, 19 or 27-bit control (during 3-wire bus mode) ? on-chip a/d converter (during i 2 c bus mode) ? on-chip high voltage drive transistor for charge pump ? reference frequency selectable from 31.25, 50 or 62.5 khz (when using a 4 mhz crystal) ? low-phase noise synthesizer ? on-chip 4-output band switch (supports output voltages from 5 to 9 v) applications ? tv tuners ? vcr tuners ? catv tuners structure bipolar silicon monolithic ic all band tv tuner ic with on-chip pll 30 pin ssop (plastic) CXA3250N this ic has the pins whose electrostatic discharge strength is weak as the operating frequency is high and the high-frequency process is used for this ic. take care of handling the ic.
2 CXA3250N block diagram and pin configuration shift register programmable divider 14/15bit divider 1/64, 80, 128 bus interface ref osc charge pump lock det if amp buffer vhf mix mode select v.reg band sw driver uhf osc vhf osc bias phase detector adc vhf mix buffer buffer uhf mix vsw 23 24 25 26 28 29 30 27 19 20 21 22 16 17 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 cl da adsw /ce bs3 bs1 bs2 bs4 v cc 1 mixout1 mixout2 gnd1 byp/ms vhfin uhfin1 uhfin2 v cc 3 refosc cpo vt lock /adc ifout gnd2 v cc 2 uoscb2 uosce2 uosce1 uoscb1 vosc2 gnd vosc1
3 CXA3250N pin description pin no. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 symbol cl da ce/adsw bs3 bs1 bs2 bs4 v cc 1 mixout1 mixou2 gnd1 byp/ms vhfin uhfin1 uhfin2 vosc1 gnd vosc2 uoscb1 uosce1 uosce2 uoscb2 v cc 2 gnd2 ifout lock/adc vt cpo refosc v cc 3 description clock/scl (i 2 c bus) data/sda (i 2 c bus) enable/address selection (i 2 c bus) band switch output 3 band switch output 1 band switch output 2 band switch output 4 analog circuit v cc mix output mix output analog circuit gnd vhf input gnd and control bus switching vhf input uhf input uhf input vhf oscillator (base input) gnd vhf oscillator (collector output) uhf oscillator (base pin) uhf oscillator (emitter pin) uhf oscillator (emitter pin) uhf oscillator (base pin) pll circuit v cc pll circuit gnd if output lock signal output/adc input (i 2 c bus) vc drive voltage output (open collector) charge pump output (loop filter connection) crystal connection band switch power supply
4 CXA3250N pin description and equivalent circuit pin symbol pin voltage equivalent circuit description no. [v] 1 2 3 4 7 5 6 8 cl da adsw/ce bs3 bs4 bs1 bs2 v cc 1 1.25 (when open) on : 4.8 off : 0.0 5.1k 5p 1 23 5.1k 5p 2 23 20 150k 50k 5p 3 23 7 30 4 6 30 5 25k 12k clock input. data input. i 2 c bus setting : address selection. bits 1 and 2 of the address byte are controlled. 3-wire bus setting : enable input. band switch outputs. the pin corresponding to the selected band goes high. analog circuit power supply.
5 CXA3250N pin symbol pin voltage equivalent circuit description no. [v] 9 10 11 12 13 14 15 16 18 17 mixout1 mixout2 gnd1 byp/ms vhfin uhfin1 uhfin2 vosc1 vosc2 gnd 3.8 during vhf reception 3.8 during uhf reception 2.4 during vhf reception 2.6 during uhf reception 2.3 during uhf reception 2.6 during vhf reception 2.3 during uhf reception 2.6 during vhf reception 2.1 during vhf reception 2.3 during uhf reception 4.2 during vhf reception 5.0 during uhf reception 9 10 24k 15p 3k 3k 76k 8 12 13 23 3k 3k 8 14 15 3k 3k 50 400 8 16 18 mixer output. these pins output the signal with open collector, and they must be connected to the power supply via the load. analog circuit gnd. pin 12 : vhf input grounding and control bus switching. pin 13 : vhf input. input format is the unbalanced input. uhf inputs. input the signal to pins 14 and 15 symmetrically or ground either of pin 14 or 15 with the capacitor and input the signal to the rest. external resonance circuit connection for vhf oscillator. gnd for separating the analog and pll systems.
6 CXA3250N pin symbol pin voltage equivalent circuit description no. [v] 19 20 21 22 23 24 25 26 uoscb1 uosce1 uosce2 uoscb2 v cc 2 gnd2 ifout lock/adc 2.1 during uhf reception 2.3 during vhf reception 1.4 during uhf reception 1.8 during vhf reception 1.4 during uhf reception 1.8 during vhf reception 2.1 during uhf reception 2.3 during vhf reception 2.8 3k 3k 8 19 20 21 22 8 25 15 250 500k 23 26 external resonance circuit connection for uhf oscillator. pll circuit power supply. pll circuit gnd. if output. i 2 c bus setting : 5-level a/d converter input. 3-wire bus setting : lock detection. low when locked, high when unlocked.
7 CXA3250N pin symbol pin voltage equivalent circuit description no. [v] 27 28 29 30 vt cpo refosc v cc 3 2.0 4.3 70 23 27 28 60k 30p 30p 29 varicap drive voltage output. this pin outputs the signal with open collector, and this must be connected to the tuning power supply via the load. charge pump output. connects the loop filter. crystal connection for reference oscillator. power supply for external supply.
8 CXA3250N electrical characteristics circuit current (v cc =5 v, ta=25 c) item circuit current a circuit current d symbol ai ccv ai ccu di cc measurement conditions v cc 1 current, band switch output open during vhf operation v cc 1 current, band switch output open during uhf operation v cc 2 current min. typ. max. unit 37 50 67 ma 39 53 71 ma 10 16 22 ma item conversion gain noise figure * 1 , * 2 1 % cross * 1 , * 3 modulation maximum output power switch on drift * 4 symbol cg1 cg2 cg3 cg4 nf1 nf2 nf3 nf4 cm1 cm2 cm3 cm4 pomax ? fsw1 ? fsw2 ? fsw3 ? fsw4 measurement conditions vhf operation f rf =55 mhz vhf operation f rf =360 mhz uhf operation f rf =360 mhz uhf operation f rf =800 mhz vhf operation f rf =55 mhz vhf operation f rf =360 mhz uhf operation f rf =360 mhz uhf operation f rf =800 mhz vhf operation f d =55 mhz, f ud =12 mhz vhf operation f d =360 mhz, f ud =12 mhz uhf operation f d =360 mhz, f ud =12 mhz uhf operation f d =800 mhz, f ud =12 mhz 50 load saturation output vhf operation f osc =100 mhz ? f from 3 s to 3 min after switch on vhf operation f osc =405 mhz ? f from 3 s to 3 min after switch on uhf operation f osc =405 mhz ? f from 3 s to 3 min after switch on uhf operation f osc =845 mhz ? f from 3 s to 3 min after switch on min. typ. max. unit 19 22 25 db 21 24 27 db 23 26 29 db 24 27 30 db 12 15 db 12 15 db 10 13 db 10 13 db 97 101 db 97 101 db 92 96 db 91 95 db +7 +10 dbm 300 khz 600 khz 350 khz 350 khz osc/mix/if amplifier block
9 CXA3250N item supply voltage * 4 drift oscillator phase noise reference leak lock-up time symbol ? fst1 ? fst2 ? fst3 ? fst4 c/n v c/n u refl lut 1 lut 2 measurement conditions vhf operation f osc =100 mhz ? f when v cc 5 v changes 5 % vhf operation f osc =405 mhz ? f when v cc 5 v changes 5 % uhf operation f osc =405 mhz ? f when v cc 5 v changes 5 % uhf operation f osc =845 mhz ? f when v cc 5 v changes 5 % 10 khz offset 10 khz offset phase comparison frequency of 62.5 khz, cp : 1 vhf operation f osc =95 mhz ? f osc =395 mhz cp : 1 uhf operation f osc =413 mhz ? f osc =847 mhz cp : 1 min. typ. max. unit 200 khz 250 khz 150 khz 150 khz 82 dbc/hz 78 55 db 34 70 ms 36 70 * 1 value measured with untuned input. * 2 nf meter direct-reading value (dsb measurement). * 3 value with a desired reception signal input level of C30 dbm, an interference signal of 100 khz/30 % am, and an interference signal level where s/i=46 db measured with a spectrum analyzer. * 4 value when the pll is not operating.
10 CXA3250N item cl, da and ce pins h level input voltage l level input voltage h level input current l level input current cpo (charge pump) output current 1 leak current 1 output current 2 leak current 2 vt (vc voltage output) maximum output voltage minimum output voltage lock h output voltage l output voltage refosc oscillation frequency range input capacitance negative resistance band sw output current saturation voltage leak current bus timing (i 2 c bus) scl clock frequency start waiting time start hold time l hold time h hold time start setup time data hold time data setup time rise time fall time stop setup time bus timing (3-wire bus) data setup time data hold time enable waiting time enable setup time enable hold time symbol v ih v il i ih i il i cpo 1 leakcp1 i cpo 2 leakcp2 v th v tl v lockh v lockl f xtosc c xtosc r neg i bs v sat leakbs f scl t wsta t hsta t low t high t ssta t hdat t sdat t r t f t ssto t sd t hd t we t se t he measurement conditions v ih =v cc v il =gnd byte4/bit6=0 byte4/bit6=0 byte4/bit6=1 byte4/bit6=1 when locked when unlocked crystal source impedance when on when on source current=20 ma when off min. typ. max. unit 3v cc v gnd 1.5 v 0 C0.1 a C2 C4 a 35 50 75 a 30 na 140 200 300 a 100 na 33 v 0.5 0.8 v v cc C0.5 v cc v 0 0.5 v 3 12 mhz 22 24 26 pf C1.4 C0.7 k C25 ma 120 240 mv 0.5 3 a 0 400 khz 1300 ns 600 ns 1300 ns 600 ns 600 ns 0 900 ns 600 ns 300 ns 300 ns 600 ns 300 ns 600 ns 300 ns 300 ns 600 ns pll block
11 CXA3250N electrical characteristics measurement circuit (i 2 c bus control) 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 CXA3250N cl da ce/adsw bs3 bs1 bs2 bs4 v cc 1 mix out1 mix out2 gnd1 byp/ms vhf in uhf in1 uhf in2 v cc 3 refosc cpo vt lock/adc ifout gnd2 v cc 2 uoscb2 uosce2 uosce1 uoscb1 vosc2 gnd vosc1 scl sda adsw fmt bvl bvh bu +5v 2 3 4 8 9 10 11 12 13 14 15 1 5 6 7 1n 1n 2.2 2k 4.5t 4.5t 56p 56p 100 1n 1n 1n vhf in uhf in 100p 1n xtal 4mhz adc in if out +5v +30v 2.2 1n 2p 7p 6p 6p 56p 56p 1p 1t363 1t363 0.5p 0.5p 47k 47k 2.6 f 2.5t 3.2 f 2.5t 20 16p 47k 1n 150p 1t362 1t363 47k 47k 47k 47k 3.2 f 5.5t 6.8k 0.047 8200p 100p 33p 22k 0.75p 1n 51 bvh 47k 1n 51 bvl 1.2k
12 CXA3250N electrical characteristics measurement circuit (3-wire bus control) 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 CXA3250N cl da ce/adsw bs3 bs1 bs2 bs4 v cc 1 mix out1 mix out2 gnd1 byp/ms vhf in uhf in1 uhf in2 v cc 3 refosc cpo vt lock/adc ifout gnd2 v cc 2 uoscb2 uosce2 uosce1 uoscb1 vosc2 gnd vosc1 scl sda enable fmt bvl bvh bu +5v 2 3 4 8 9 10 11 12 13 14 15 1 5 6 7 1n 1n 2.2 2k 4.5t 4.5t 56p 56p 100 1n 1n 1n 1n vhf in uhf in 100p 1n xtal 4mhz adc in if out +5v +30v 2.2 1n 2p 7p 6p 6p 56p 56p 1p 1t363 1t363 0.5p 0.5p 47k 47k 2.6 f 2.5t 3.2 f 2.5t 20 16p 47k 1n 150p 1t362 1t363 47k 47k 47k 47k 3.2 f 5.5t 6.8k 0.047 8200p 100p 33p 22k 0.75p 1n 51 bvh 47k 1n 51 bvl 1.2k
13 CXA3250N application circuit (i 2 c bus control) CXA3250N cl da ce/adsw bs3 bs1 bs2 bs4 v cc 1 mix out1 mix out2 gnd1 byp/ms vhf in uhf in1 uhf in2 v cc 3 refosc cpo vt lock/adc ifout gnd2 v cc 2 uoscb2 uosce2 uosce1 uoscb1 vosc2 gnd vosc1 scl sda adsw fmt bu 2 3 4 8 9 10 11 12 13 14 15 1 5 6 7 1n 2k 450nh 28p 100 100p 1n 2p vhf uhf 100p 10p xtal 4mhz +30v 1n 3p 15p 16p 6p 1n 1n 1p 1t363 0.5p 10k 2 f 1.5t 3.2 f 2.5t 20 16p 10k 1n 100p 1t362 1t363 10k 10k 10k 47k 3.2 f 5.5t 6.8k 0.047 8200p 100p 22k 0.75p 1n 1.2k 47k 1n 1.2k 51 2.2 10k 10n 10 if out 1.2 2p 2.2n 2.2n 2.2n bvl bvh 2.2 +5v 3k 56p 56p 1n 220 220 6.8 h 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 application circuits shown are typical examples illustrating the operation of the devices. sony cannot assume responsibility fo r any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same .
14 CXA3250N application circuit (3-wire bus control) CXA3250N cl da ce/adsw bs3 bs1 bs2 bs4 v cc 1 mix out1 mix out2 gnd1 byp/ms vhf in uhf in1 uhf in2 v cc 3 refosc cpo vt lock/adc ifout gnd2 v cc 2 uoscb2 uosce2 uosce1 uoscb1 vosc2 gnd vosc1 scl sda enable fmt bu 1n 2k 450nh 28p 100 100p 1n 2p vhf uhf 100p 10p xtal 4mhz +30v 1n 3p 15p 16p 6p 1n 1n 1p 1t363 0.5p 10k 2 f 1.5t 3.2 f 2.5t 20 16p 10k 1n 100p 1t362 1t363 10k 10k 10k 47k 3.2 f 5.5t 6.8k 0.047 8200p 100p 22k 0.75p 1n 1.2k 47k 1n 1.2k 51 2.2 10k 10n 10 if out 1.2 2p 2.2n 2.2n 2.2n bvl bvh 2.2 +5v 3k 56p 56p 1n 220 220 6.8 h 1n 2 3 4 8 9 10 11 12 13 14 15 1 5 6 7 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 application circuits shown are typical examples illustrating the operation of the devices. sony cannot assume responsibility fo r any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same .
15 CXA3250N description of functions the CXA3250N is a ground wave broadcast tuner ic which converts frequencies to if in order to tune and detect only the desired reception frequency of vhf, catv and uhf band signals. in addition to the mixer, local oscillation and if amplifier circuits required for frequency conversion to if, this ic also integrates a pll circuit for local oscillation frequency control onto a single chip. the functions of the various circuits are described below. 1. mixer circuit this circuit outputs the frequency difference between the signal input to vhfin or uhfin and the local oscillation signal. 2. local oscillation circuit a vco is formed by externally connecting an lc resonance circuit composed of a varicap diode and inductance. 3. if amplifier circuit this circuit amplifies the mixer if output, and consists of an amplifier stage and low impedance output stage. 4. pll circuit this pll circuit fixes the local oscillation frequency to the desired frequency. it consists of a programmable divider, reference divider, phase comparator, charge pump and reference oscillator. the control format supports both the i 2 c bus and 3-wire bus formats. during i 2 c bus control, the frequency steps of 31.25, 50 or 62.5 khz can be selected by the data-based reference divider frequency division setting value. during 3-wire bus control, these frequency steps can be selected by the combination of the communication word length (18 or 19 bits) and the voltage applied to the byp/ms pin. 5. band switch circuit the CXA3250N has four sets of built-in pnp transistors for switching between the vl, vh and uhf bands and for switching the fm trap, etc. these pnp transistors can be controlled by the bus data. the emitters for these pnp transistors are connected to an independent power supply pin (v cc 3) from the oscillator, mixer and pll circuits, and support either 5 v or 9 v as the rf amplifier power supply.
16 CXA3250N description of analog block operation (see the electrical characteristics measurement circuit.) vhf oscillator circuit ? this circuit is a differential amplifier type oscillator circuit. pin 18 is the output and pin 16 is the input. oscillation is performed by connecting an lc resonance circuit including a varicap to pin 18 via coupled capacitance, inputting to pin 16 with feedback capacitance, and applying positive feedback. ? the amplifier between pins 16 and 18 has an extremely high gain. therefore, care should be taken to avoid creating parasitic capacitance, resistance or other feedback loops as this may produce abnormal oscillation. vhf mixer circuit ? the mixer circuit employs a double balanced mixer with little local oscillation signal leakage. the input format is base input type, with pin 12 grounded via a capacitor and the rf signal input to pin 13. (pin 12 can also be used to switch the pll mode according to the applied dc voltage value.) ? the rf signal is fed from the oscillator, converted to if frequency and output from pins 9 and 10. uhf oscillator circuit ? this oscillator circuit is designed so that two collector ground type colpitts oscillators perform differential oscillation operation via an lc resonance circuit including a varicap. ? resonance capacitance is connected between pins 19 and 20, pins 20 and 21, and pins 21 and 22, and an lc resonance circuit including a varicap is connected between pins 19 and 22. uhf mixer circuit ? this circuit employs a double balanced mixer like the vhf mixer circuit. the input format is base input type, with pins 14 and 15 as the rf input pins. the input method can be selected from balanced input consisting of differential input to pins 14 and 15 or unbalanced input consisting of grounding pin 14 via a capacitor and input to pin 15. ? pins 9 and 10 are the mixer outputs. if amplifier circuit ? the signals frequency converted by the mixer are output from pins 9 and 10, and at the same time are ac coupled inside the ic and input to the if amplifier. ? single-tuned filters are connected to pins 9 and 10 in order to improve the interference characteristics of the if amplifier. ? the signal amplified by the if amplifier is output from pin 25. the output impedance is approximately 75 .
17 CXA3250N description of pll block this ic supports both i 2 c bus and 3-wire bus control. the i 2 c bus conforms to the standard i 2 c bus format, and bidirectional bus control is possible consisting of a write mode in which various data are received and a read mode in which various data are sent. the 3-wire bus is equipped with an 18- or 19-bit auto identify function, and the frequency step can be switched according to the voltage applied to the byp/ms pin. the pll of this ic does not have a fixed frequency division circuit and performs high-speed phase comparison, providing low reference leak and quick lock-up time characteristics. during power-on (v cc 2), the power-on reset circuit operates to initialize the frequency data to all 0 and the band data to all off. power-on reset is performed when vcc2=2.5 v at room temperature (ta=25 c). pin function table 1.) pll mode setting method the selected control bus is set according to the byp/ms pin (pin 12) voltage. during 3-wire bus control, the transferred bit length (18, 19 or 27 bits) is automatically identified. during 18- or 19-bit transfer, the frequency steps in the table below are set according to the combination of the byp/ms pin voltage and the bit length. this ic does not have a fixed frequency division circuit, so the phase comparison frequency becomes the frequency step. symbol cl da adsw/ce lock/adc i 2 c bus scl input sda i/o address selection adc input 3-wire bus clock input data input enable input lock output byp/ms pin gnd open v cc control bus i 2 c bus 3-wire bus 3-wire bus byp/ms pin voltage open open open or v cc v cc v cc transfer bit length 18 19 27 18 19 reference divider 64 128 selectable from 64, 80 or 128 80 80 phase comparison frequency 62.5 khz 31.25 khz 62.5 khz/ 50.0 khz/ 31.25 khz 50.0 khz 50.0 khz frequency step * 62.5 khz 31.25 khz 62.5 khz/ 50.0 khz/ 31.25 khz 50.0 khz 50.0 khz * phase comparison frequency and frequency step are for when the crystal oscillation=4 mhz.
18 CXA3250N 2.) programming the vco lock frequency is obtained according to the following formula. fosc=fref (32 m + s) fosc : local oscillator frequency fref : phase comparison frequency m : main divider frequency division ratio s : swallow counter frequency division ratio the variable frequency division ranges of m and s are as follows, and are set as binary. s < m 1023 (s < m 511 during 18-bit transfer) 0 s 31 3.) i 2 c bus control this ic conforms to the standard i 2 c bus format, and bidirectional bus control is possible consisting of a write mode in which various data are received and a read mode in which various data are sent. write and read modes are recognized according to the setting of the final bit (r/w bit) of the address byte. write mode is set when the r/w bit is 0 and read mode is set when the r/w bit is 1.
19 CXA3250N 3-1) address settings up to four addresses can be selected by the hardware bit settings, so that multiple pll can exist within one system. the responding address can be set according to the adsw/ce pin voltage. address hardware bits 3-2) write mode write mode is used to receive various data. in this mode, byte 1 contains the address data, bytes 2 and 3 contain the frequency data, byte 4 contains the control data, and byte 5 contains the band switch data. these data are latch transferred in the manner of byte 1, byte 2 + byte 3, and byte 4 + byte 5. when the correct address is received and acknowledged, the data is recognized as frequency data if the first bit of the next byte is 0, and as control data and band switch data if this bit is 1. also, when data transmission is stopped part-way, the previously programmed data is valid. therefore, once the control and band switch data have been programmed, 3-byte commands consisting of the address and frequency data are possible. further, even if the i 2 c bus stop conditions are not met, data can be input by sending the start conditions and the new address. 1 1 0 0 0 ma1 ma0 r/w ce pin voltage 0 to 0.1 v cc open or 0.2 v cc to 0.3 v cc 0.4 v cc to 0.6 v cc 0.9 v cc to v cc ma1 0 0 1 1 ma0 0 1 0 1
20 CXA3250N the control format is as shown in the table below. write-mode : slave receiver mode address byte divider byte 1 divider byte 2 control byte band sw byte msb lsb bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 1 1 0 0 0 ma1 ma0 0 a 0 m9m8m7m6m5m4m3 a m2 m1 m0 s4 s3 s2 s1 s0 a 1cp0cdxr1r0osa x x x x bs4 bs3 bs2 bs1 a x : dont care a : acknowledge bit ma0, ma1 : address setting m0 to : main divider frequency division ratio setting s0 to : swallow counter frequency division ratio setting cd : charge pump off (when 1) os : varicap output off (when 1) cp : charge pump current switching (200 a when 1, 50 a when 0) bs1 to bs4 : band switch control (output pnp transistor on when 1) r0, r1 : reference divider frequency division ratio setting. see the reference divider frequency division ratio table. reference divider frequency division ratio table reference divider 128 64 80 r1 0 1 x r0 1 1 0 x : dont care
21 CXA3250N 3-3) read mode in read mode, the phase comparator locked/unlocked status and 5-level a/d converter input pin voltage status are transmitted and output to the master. the read data format is as shown in the table below. read mode : slave transmitter a : acknowledge bit ma0, ma1 : address setting fl : lock detection signal (1: locked, 0: unlocked) a0 to a1 : a/d converter (see the table below.) 5-level a/d converter output table mode address byte status byte bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 1 1 0 0 0 ma1 ma0 0 a x fl 1 1 1 a2 a1 a0 a voltage applied to lock/adc pin 0.6 v cc 2 to v cc 2 0.45 v cc 2 to 0.6 v cc 2 0.3 v cc 2 to 0.45 v cc 2 0.15 v cc 2 to 0.3 v cc 2 0 to 0.15 v cc 2 a1 1 0 0 0 0 a1 0 1 1 0 0 a0 0 1 0 1 0
22 CXA3250N 4.) 3-wire bus control the following transfer bit length formats are automatically identified during 3-wire bus control. 18 bits : band data (4 bits) + frequency data (14 bits) 19 bits : band data (4 bits) + frequency data (15 bits) 27 bits : band data (4 bits) + frequency data (15 bits) + test data (8 bits) 4-1) 18-bit data transfer data is loaded at the rising edge of the clock signal while the enable signal is high, and is latched at the falling edge of the enable signal. the clocks during the enable period are counted, and when 18 bits have been loaded, the programmable divider m9 data is set to 0 and the reference divider frequency division ratio is automatically set to 1/80 when the byp/ms pin voltage is v cc or to 1/64 when the byp/ms pin is dc open. 4-2) 19-bit data transfer data is loaded at the rising edge of the clock signal while the enable signal is high, and is latched at the falling edge of the enable signal. the clocks during the enable period are counted, and when 19 bits have been loaded, the reference divider frequency division ratio is automatically set to 1/80 when the byp/ms pin voltage is v cc or to 1/128 when the byp/ms pin is dc open. 145 18 bs4 bs3 bs2 bs1 m8 m7 m6 m5 m4 m3 m2 m1 m0 s4 s3 s2 s1 s0 data clock enable time latch invalid data invalid data band switch data frequency data 18-bit data format 145 19 bs4 bs3 bs2 bs1 m8 m9 m7 m6 m5 m4 m3 m2 m1 m0 s4 s3 s2 s1 s0 data clock enable time latch invalid data invalid data band switch data frequency data 19-bit data format
23 CXA3250N 4-3) 27-bit data transfer the 3-wire bus also automatically supports the 27-bit format in which various control data are transferred in addition to the band and frequency data. data is loaded at the rising edge of the clock signal while the enable signal is high, and is latched at the falling edge of the enable signal. the clocks during the enable period are counted, and 27 bits of data as counted from the rising edge of the enable signal are loaded as valid data. m0 to : main divider frequency division ratio setting s0 to : swallow counter frequency division ratio setting cd : charge pump off (when 1) os : varicap output off (when 1) cp : charge pump current switching (200 a when 1, 50 a when 0) bs1 to bs4 : band switch control (output pnp transistor on when 1) r0, r1 : reference divider frequency division ratio setting. reference divider frequency division ratio table 145 27 19 20 bs4 bs3 bs2 bs1 m8 m9 s3 s2 s1 s0 x cp cd x r1 r0 x data clock enable time latch invalid data invalid data band switch data frequency data test data 27-bit data format reference divider 128 64 80 r1 0 1 x r0 1 1 0 x : dont care
24 CXA3250N i 2 c bus timing chart 3-wire bus timing chart t wsta t ssta t hsta t low t high t sdat t hdat t r t f t ssto start stop clock datachange t ssta =start setup time t wsta =start waiting time t hsta =start hold time t low =low clock pulse width t high =high clock pulse width t sdat =data setup time t hdat =data hold time t ssto =stop setup time t r =rise time t f =fall time sda scl t hd t sd t sd =data setup time t hd =data hold time t se =enable setup time t he =enable hold time t we =enable waiting time data clock enable 3v 1.5v 3v 1.5v 3v 1.5v t we t he t se
25 CXA3250N example of representative characteristics circuit current vs. supply voltage 1 ai cc -circuit current [ma] v cc 1-supply voltage [v] 60 58 56 54 52 50 48 46 44 42 40 4.7 4.8 4.9 5 5.1 5.2 5.3 5.4 uhf vhf i/o characteristics (untuned input) if output level [dbm] rf level [dbm] 20 0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 0 10 20 circuit current vs. supply voltage 2 di cc -circuit current [ma] v cc 2-supply voltage [v] 20 15 10 4.7 4.8 4.9 5 5.1 5.2 5.3 5.4 band sw output voltage vs. output current (bs1, bs2, bs3, bs4) output voltage [v] output current [ma] 9.2 9.0 8.8 8.6 5.0 4.8 4.6 4.4 0 5 10 15 20 25 v cc 3=9v v cc 3=5v band sw output voltage vs. output current output voltage [v] output current [ma] 9.2 9.0 8.8 8.6 5.0 4.8 4.6 4.4 0123456 f rf =100mhz (vhf) f rf =450mhz (uhf) f if is both f=45mhz v cc 3=9v v cc 3=5v
26 CXA3250N conversion gain vs. reception frequency (untuned input) cg-conversion gain [db] reception frequency [mhz] 40 30 20 10 0 0 100 300 200 400 500 600 700 800 900 uhf uhf f if =45mhz next adjacent cross modulation vs. reception frequency (untuned input) cm-cross modulation [db ] reception frequency [mhz] 120 80 100 60 40 20 0 0 100 300 200 400 500 600 700 800 900 noise figure vs. reception frequency (untuned input, in dsb) nf-noise figure [db] reception frequency [mhz] 20 15 10 5 0 0 100 300 200 400 500 600 700 800 900 uhf vhf (low) vhf (high) vhf (low) vhf (high) f if =45mhz f if =45mhz f ud =f d +12mhz f ud =f d ?2mhz (100khz, 30%am) pcs beat characteristics if output level [dbm] sg output level [dbm] (f p level) +20 0 +10 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 0 +10 +20 oscillation frequency power supply fluctuation (pll off) +b drift [khz] 400 oscillation frequency [mhz] 100 200 300 0 ?00 ?00 ?00 ?00 0 100 300 200 400 500 600 700 800 900 v cc +5% v cc ?% (v cc =5v) vhf (low) vhf (high) f beat f if f local =129mhz f p =83.25mhz f c =86.83mhz (f p ?2db) f s =87.75mhz (f p ?.7db) f if =45.75mhz f beat =f if 920khz
27 CXA3250N tuning response time 1 vhf (low) 95mhz ? vhf (high) 395mhz cp=1 ?0,0000ms 10,0000ms 10,0ms/div 60,0000ms real time 5.0v/div offset 10.0v t=34msec cp=0 ?30,000ms 20,0000ms 30,0ms/div 170,000ms real time 5.0v/div offset 10.0v t=68msec
28 CXA3250N tuning response time 2 uhf 413mhz ? uhf 847mhz cp=1 ?0,0000ms 10,0000ms 10,0ms/div 60,0000ms real time 5.0v/div offset 10.0v t=36msec cp=0 ?0,0000ms 30,0000ms 20,0ms/div 130,000ms real time 5.0v/div offset 10.0v t=87msec
29 CXA3250N tuning response time 3 vhf (high) 395mhz ? vhf (low) 95mhz cp=1 ?0,0000ms 10,0000ms 10,0ms/div 60,0000ms real time 5.0v/div offset 10.0v t=22msec cp=0 ?00,000ms 0,00000s 20,0ms/div 100,000ms real time 5.0v/div offset 10.0v t=34msec
30 CXA3250N tuning response time 4 uhf 847mhz ? uhf 413mhz cp=1 ?0,0000ms 10,0000ms 20,0ms/div 110,000ms real time 5.0v/div offset 10.0v t=20msec cp=0 ?00,000ms 0,00000s 20,0ms/div 100,000ms real time 5.0v/div offset 10.0v t=50msec
31 CXA3250N if output spectrum center 45.0mhz #res bw 1.0khz span 100.0khz swp 30.0 sec #vbw 10hz 10db/div vhf (low) f rf =55mhz f l.0 =100mhz rf input level : ?0dbm if output spectrum center 45.0mhz res bw 1.0khz span 100.0khz swp 30.0 sec #vbw 10hz 10db/div vhf (high) f rf =350mhz f l.0 =395mhz rf input level : ?0dbm
32 CXA3250N if output spectrum center 45.0 270mhz #res bw 1.0khz span 100.0khz swp 30.0 sec #vbw 10hz 10db/div uhf f rf =800mhz f l.0 =845mhz rf input level : ?0dbm
33 CXA3250N vhf input impedance j100 j50 j25 0 ?25 ?50 ?100 50 1000p s11 byp/ms vhfin 50mhz 350mhz 12 13 uhf input impedance j100 j50 j25 0 ?25 ?50 ?100 50 s11 uhfin1 uhfin2 350mhz 800mhz 14 15
34 CXA3250N if output impedance j100 j50 j25 0 ?25 ?50 ?100 50 45mhz 38mhz
sony code eiaj code jedec code package structure package material lead treatment lead material package mass epoxy resin solder/palladium 42/copper alloy 30pin ssop (plastic) * 9.7 0.1 * 5.6 0.1 0.65 0.22 ?0.05 30 115 16 1.25 + 0.2 ?0.1 7.6 0.2 0.15 + 0.05 ?0.02 0.1 0.1 0.5 0.2 0?to 10 a detail a ssop-30p-l01 ssop030-p-0056 0.1g note: dimension * ?does not include mold protrusion. plating 0.10 0.13 m + 0.1 package outline unit : mm CXA3250N 35 note : palladium plating this product uses s-pdppf (sony spec.-palladium pre-plated lead frame).

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